1. Field of the Invention
The present invention relates to a semiconductor memory device and, in particular, an improvement in a chip layout of a memory cell array.
2. Description of the Related Art
A conventional semiconductor memory device, such as a dynamic RAM (hereinafter referred to as a DRAM) and static RAM (hereinafter referred to as SRAM), has a chip layout as shown in FIG. 1.
A memory cell array area 12 is formed at the central area of a semiconductor chip 11. An area 13 other than a peripheral circuit area, bonding pad area and input protection circuit, is formed at an outer marginal portion of the memory cell array 12. A row decoder 14 is formed relative to a row direction of the memory cell array area 12 and a column decoder 15 is formed relative to the column direction of the memory cell array area 12.
The chip layout of the DRAM or SRAM is broadly divided into the memory cell array area 12 and the rest, that is the area 13, of the chip layout. The memory cell array area 12 includes memory cell arrays regularly arranged relative to a word line (WL) or bit line (BL), decoders for selecting the memory cell arrays, sense amplifier for amplifying data supplied from the memory cell array, and so on. The area 13 includes an irregular peripheral circuit which is not formed for each WL and BL, and so on.
An increase in size of the memory cell array area 12 is caused due to an increase in capacity of memory. In a DRAM or SRAM of the aforementioned chip layout, there is a large increase in resistance and capacitance at a location of WL and BL. That is, a large increase in the resistance and capacitance leads to a signal delay on WL and BL and a further increase in charging/discharging current I.sub.BL on BL.
In connection with a signal delay on WL and BL, let it be assumed that the connection length l of WL and BL is doubled due to an increase in size of, for example, a memory cell array. In this case, the resistance R (.varies.l) is doubled at WL and BL and the capacitance C (.varies.l) is doubled there. Since the signal delay time td is proportional to the resistance R and capacitance C, the signal delay at WL and BL is increased by a factor of 4. Stated in another way, when the connection length l is increased by a factor of n, then a signal transmission is delayed by a factor of n.sup.2.
In connection with an increase in the charging/discharging current I.sub.BL at BL, let it be assumed that, for example, a capacitance C.sub.B is doubled at BL. In this case, the charging/discharging current I.sub.BL is doubled at BL because it is proportional to the capacitance C.sub.B. That is, ##EQU1## where t.sub.RC denotes a cycle time; Q, an amount of charge; V, a voltage; SA number, the number of sense amplifiers; I, an operation current; and I.sub.peri, a dissipation current at the peripheral circuit area.
As will be appreciated from the above, a factor-of-n increase in the capacitance C.sub.B at BL results in a factor-of-n increase in the charging/discharging current I.sub.BL . It is to be noted that an increase in the charging/discharging current I.sub.BL serves additively as an operation current I.
In this way, a signal delay at WL and BL prevents achievement of a high-speed semiconductor memory device and causes an operation error at a subsequent circuit. This problem is common to all the connection lines irrespective of WL and BL.
Further, an increase in the charging/discharging current I.sub.BL exerts a greater influence on the characteristic of the device because 60 to 70% of the operation current I is governed by the charging/discharging current I.sub.BL.
It is known that, if the memory cell array area 12 is located at the central area of a semiconductor chip with the rest of the chip, that is the area 13, arranged as a peripheral area, the peripheral circuit blocks increase in number. The increase in the number of the peripheral circuit blocks increases a dissipation current I.sub.peri there and hence an operation current I correspondingly increases, adversely affecting the characteristic of the device.